Interface Module Types
(MINI-MODULES)

MINI-PANAVIA/T4:
The MINI-PANAVIA/T4 module interface comprises of four independent transmitter
channels that act as bus traffic simulators.
The constituent parts of the module comprise of Line drivers for transmitting
differential clock and data to a PANAVIA databus, a proprietary FPGA transmitter
circuit, a dual port RAM for interface to the local bus and a
Microcontroller executing the transmitter firmware.
All transmitted data is retrieved from the dual port RAM by the microprocessor
and sent to the FPGA circuit for transmission. The data is transmitted as
standard 32 bit data with the Tag, Control bits and data fields in their correct
positions as defined in the PANAVIA specification. The Parity is generated and
set to Odd as per the PANAVIA data standard.
The MINI-PANAVIA/T4 executes autonomously instructions held in the interface
memory. For each simulated PANAVIA transmitter all Tags can be generated or
alternatively just a sub-set group of Tags can be generated. Tag data
descriptors can be updated during simulation at any time without corrupting the
transmission.
MINI-PANAVIA/R4:
The MINI-PANAVIA/R4 receiver module contains four receivers.
The constituent parts of the module comprise of line
receivers for accepting differential clock and data from a PANAVIA databus, a
proprietary FPGA receiver circuit, a dual port RAM for interface to the
local bus and a Microcontroller executing the receiver firmware.
All received data is processed by the microprocessor and
stored in the dual port RAM according to channel numbers and Tag value. The data
is stored in raw 26-bit form with the Tag, Control bits and data field left in
their correct position as defined in the PANAVIA specification. The Parity is
not checked, but is relayed to the user in it’s original state so that the user
can have the option of checking this and deciding what to do about Parity
errors, etc.
A channel Status register provides information to the user about the state of the PANAVIA clock for each
interrogated channel. This ensures that the data
being retrieved is ‘live’ data and not static left over from a previous bus
activity session.
All units are designed to
meet the European and US EMC regulations.
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