Click here to download PCI-MAXI/MINI-T2/R2 'C' Driver Library (Version 2.3 / June 2003) for Windows 95 / 98 / NT4 / W2K (later operating systems, including XP, will also be supported – check with YED for further information) and the User Manual. (File size: 1,460kB)
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MINI-429/T4:

The MINI-429/T4 ARINC 429 Interface has four independent transmitter channels acting as Bus Traffic Simulators. The functions on the four channels are available concurrently at full performance level. The card contains a microprocessor, Dual Port and ARINC 429 line drivers.
 

MINI-429/R4:

The MINI-429/R4 ARINC 429 Interface has four independent receiver channels providing advanced Monitor and Analyser functions. The functions on the four channels are available concurrently at full performance level. In addition to this the card also contains, a microprocessor, a time tag register, 28 volt Event input, Opto-coupled inputs, Automatic Rx bit-rate reception, Data Acquisition FIFO's, and Dual Port. The card will filter from all 256 label/SDI combinations.
 

MINI-PANAVIA/T4:

The MINI-PANAVIA/T4 module interface comprises of four independent transmitter channels that act as bus traffic simulators.

The constituent parts of the module comprise of Line drivers for transmitting differential clock and data to a PANAVIA databus, a proprietary FPGA transmitter circuit, a dual port RAM for interface to the local bus and a Microcontroller executing the transmitter firmware.

All transmitted data is retrieved from the dual port RAM by the microprocessor and sent to the FPGA circuit for transmission. The data is transmitted as standard 32 bit data with the Tag, Control bits and data fields in their correct positions as defined in the PANAVIA specification. The Parity is generated and set to Odd as per the PANAVIA data standard.

The MINI-PANAVIA/T4 executes autonomously instructions held in the interface memory. For each simulated PANAVIA transmitter all Tags can be generated or alternatively just a sub-set group of Tags can be generated. Tag data descriptors can be updated during simulation at any time without corrupting the transmission.
 

MINI-PANAVIA/R4:

The MINI-PANAVIA/R4 receiver module contains four receivers.

The constituent parts of the module comprise of line receivers for accepting differential clock and data from a PANAVIA databus, a proprietary FPGA receiver circuit, a dual port RAM for interface to the local bus and a Microcontroller executing the receiver firmware.

All received data is processed by the microprocessor and stored in the dual port RAM according to channel numbers and Tag value. The data is stored in raw 26-bit form with the Tag, Control bits and data field left in their correct position as defined in the PANAVIA specification. The Parity is not checked, but is relayed to the user in it’s original state so that the user can have the option of checking this and deciding what to do about Parity errors, etc.

A channel Status register provides information to the user about the state of the PANAVIA clock for each interrogated channel. This ensures that the data being retrieved is ‘live’ data and not static left over from a previous bus activity session.