ARINC 429 12 Channel CPU with Serial Bus
The YED/A429-R8-T4-CPU, when used in conjunction with the YED/A429-R8-T8-FPGA, forms a complete multi-channel ARINC 429 interface.
The CPU is controlled via a simple 5-byte serial communications protocol, which in turn controls the various functions of the FPGA. The advantage of this arrangement is that no detailed knowledge of the FPGA is required leaving the programmer free to concentrate on peforming the required ARINC 429 operations.
All units are designed to meet the European and US EMC regulations.
ARINC 429 12 Channel CPU with Serial Bus Detail
The firmware within the CPU contains all the necessary intelligence to set up filtering of received data, updating of transmitted data and management of periodic table transmissions. Reception of ARINC 429 data is automatically handled without the user needing to know the bit rate (12.5/100kHz) of the incoming data. There is no requirement to set or check the parity of transmitted or received data, or to flip the bit order of the ARINC 429 Label field, etc. All of these requirements are taken care of by the FPGA.
The YED/A429-R8-T8-FPGA contains 8x ARINC 429 Transmitter and 8x ARINC 429 Receiver channels. The CPU is a Cortex-M3 STM32 processor, which is used in our YED/A429-R8-T4 Serial Module. When the CPU and the FPGA are used together they form a flexible, but powerful, ARINC 429 interface that can be easily integrated into your own product or system.
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ARINC 429 12 Channel CPU with Serial Bus Specifications
- STM32 CPU with Serial <=> ARINC429 firmware.
- Comms protocol for 8-Channel ARINC 429 Receiver.
- Comms protocol for 4-Channel ARINC 429 Transmitter.
- Interfaces directly to YED/A429-R8-T4-FPGA.
- Simple 5-Byte Serial Communications protocol.
- USART baud rate: 115200, 921k and 1.8M.
- 8-Data bits, 2-Stops bits with/without Parity
- Optional Hardware (CTS/RTS) handshaking.
- 16MHz external clock required.
ARINC 429 12 Channel CPU with Serial Bus Downloads
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