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In Detail


The YED/A429-R8-T8 FPGA has been designed for applications that require an ARINC 429 interface. This FPGA is used in our YED/A429-R8-T4 Serial Module and contains eight ARINC 429 receiver channels and four ARINC 429 transmitter channels - all of which are totally independent from one another.

The essential components of the ARINC 429 FPGA are the ARINC 429 Transmitters, Receivers, Control registers and Status registers, all of which are accessible to a CPU as externally memory mapped registers.

The FPGA contains a memory mapped CPU interface (FSMC) configured for use with ARM Cortex-M3 processors and this has been fully tested on the STM32F103 processor. For further information on this processor please refer to A429-STM32 page.

The FPGA design has been coded in VHDL and the resultant model has been fully simulated. The FPGA is available in a variety of transmitter/receiver configurations and package types.

All units are designed to meet the European and US EMC regulations.

ARINC 429 IP / FPGA Detail

ARINC 429 Transmitter
Each ARINC 429 transmitter channel contains its own internal 128x32-bit level FIFO. Transmission will commence as soon as a 32-bit ARINC 429 word is written to the selected channel FIFO. Transmission will continue until the FIFO becomes Empty. The FIFO status (Empty/Full) can be checked by reading the FIFO status register. If the FIFO becomes full, any additional data written will be discarded.

The FPGA handles automatic insertion of the required 4-bit inter-word-gap (IWG) period between transmitted words. Transmitted and Received ARINC 429 Labels have their bit order flipped automatically thus relieving the programmer from having to perform this task. Transmitted and received parity is automatically handled and can be set to ODD, EVEN or No Parity.

ARINC 429 Receiver
The ARINC 429 receivers receive data from the ARINC 429 bus and perform a serial-to-parallel conversion. During this process the inter-word-gap (IWG) and parity are checked. Any data that does not contain the correct Parity or the correct number of bits will be ignored. A noise filtering mechanism has been implemented to enhance the receiver robustness and improve bit decoding.

In 1988, YED was the first company to incorporate automatic bit rate detection on reception of ARINC 429 data. This FPGA design also incorporates this feature and relieves the user from having to set the receiver to low or high bit rate prior to receiving data. This mechanism prevents data word over runs from occuring.

As with the transmitter, the Label field of the received data is automatically flipped to save the user from having to perform this operation. Receiver Parity can be set to Odd, Even or None.

Please feel free to contact our Sales people for further information or to submit details of your requirement, by e-mailing sales@yed.com.

ARINC 429 IP / FPGA Specifications

  • 8-Channel ARINC 429 Receiver.
  • 8-Channel ARINC 429 Transmitter.
  • 128x32 deep internal Transmit FIFO per channel.
  • Separate channels for ARINC 429 Tx and Rx.
  • Programmable Tx bit rate per channel (12.5/100 kHz).
  • Programmable parity: Even, Odd or No-parity.
  • Optimised for interface to Cortex-M3 32-bit processor.
  • Automatic Label flipped bit order on Tx and Rx.
  • Receiver automatically adapts to incoming bit rate.

All units are designed to meet the European and US EMC regulations.

ARINC 429 IP / FPGA Downloads

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